1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor structure, and more particularly, to a method of fabricating a semiconductor structure for preventing a patterned resist from being poisoned and improving the control of the critical dimension.
2. Description of the Prior Art
The development of semiconductor integrated circuit technology progresses continuously and circuit designs in products of the new generation become smaller and more complicated than those of the former generation. The amount and the density of the functional devices in each chip region are increased constantly according to the requirements of innovated products, and the size of each device has to become smaller accordingly.
In conventional methods of forming contact holes, a photo resist layer serves as an etching mask for etching the underlying interlayer dielectric layer. However, as the density of semiconductor devices on a wafer is increasing, the intervals between the devices are becoming shorter and shorter, and it becomes more difficult to form the contact holes because of the exposure resolution limitation. Accordingly, the current solution is to use a double-exposure patterning technology to create desired contact holes. In the double-exposure patterning technology, the photo resist of the second lithographic process tends to be poisoned and/or contaminated by compositions of other material layers exposed by the first lithographic process, and the critical dimension of the second lithographic process may be affected accordingly.